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Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies

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2 Author(s)
Jiale Liang ; Department of Electrical Engineering, Stanford University, Stanford , CA, USA ; H. -S. Philip Wong

Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of a resistive cross-point memory array under the worst-case write and read operations. We focus on the data pattern dependence of the memory array and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size. The number of cells in the array can reach 106 with a signal swing > 50% of the reading voltage when Ron is beyond 3 M and Roff/Ron is greater than 2. A large memory cell resistance value can further reduce the power consumption, obviate the need for a large Roff/Ron ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I -V characteristics of the memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design.

Published in:

IEEE Transactions on Electron Devices  (Volume:57 ,  Issue: 10 )