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Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon–Germanium Source/Drain

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12 Author(s)
Sophie Baudot ; Equipe Mixte CEA-CNRS “Nanophysique et Semiconducteurs,” SP2M, INAC, CEA , Grenoble Cedex 9, France ; Francois Andrieu ; Olivier Weber ; Pierre Perreau
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Strained p-MOSFETs with recessed and embedded silicon-germanium (eSiGe) source/drain (S/D) are fabricated on either silicon-on-insulator (SOI) or strained SOI (sSOI) substrates of 15-nm body thickness. For a gate voltage overdrive of -1 V and a gate length L of 60 nm, p-MOSFETs on SOI (sSOI) with eSiGe exhibit a 37% (18%) saturation drive current enhancement compared to standard sSOI structures with Si S/D. The low field mobility and series resistance are extracted in order to understand the performance boost induced by the eSiGe process. The significant I_ON improvement of SOI pMOS with eSiGe S/D compared to sSOI pMOS with Si S/D is attributed to a 65% mobility enhancement and to a 30% series-resistance reduction with respect to sSOI pMOS with Si S/D at L = 60 nm.

Published in:

IEEE Electron Device Letters  (Volume:31 ,  Issue: 10 )