Skip to Main Content
This paper presents a kind of reliable low-leakage cache - RC-Cache, to solve the problem of high soft error rate in low-leakage on-chip caches. The proposed structure combines circuit technique and micro-architecture technique, and can reduce impacts of soft errors on leakage power optimization technique of caches. At circuit level, we improve the soft error immune of SRAM through specially designed soft error immune SRAM cell - SI-SRAM; at microarchitecture level, we reduce the soft error vulnerability of low-leakage caches by burst-based access prediction and early write-back operation. Experimental results show that in normal mode, soft error rate of RC-Cache is only 1/7 of the conventional cache, and in drowsy mode it is just 2/5. The techniques significantly improve the reliability of caches and, to a certain extent, mitigate soft error problem of low-leakage on-chip caches.