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Tunnel Field Effect Transistor (TFET) is an emerging ultra-low power transistor that can, in principle, exhibit <;60mV/dec slope. While a limited number of 1-dimensional analytical modeling work have been reported till date, the influence of drain bias on the transistor characteristics is not included in these models. In this work, we present a 2-dimensional analytical model of double gate ultra thin body TFET (Fig. 1) taking into consideration the influence of the drain bias. Based on this model, we show that the Tunnel FETs exhibit superior short channel effects than their MOSFET counterparts at comparable dimensions, but the scalability of the former degrades at a faster rate with gate length scaling.
Device Research Conference (DRC), 2010
Date of Conference: 21-23 June 2010