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This paper presents a method for fast, automated analysis of device constraints in analog CMOS circuits. A linearized operating point (LOP) model is proposed which allows device constraints like saturation conditions to be formulated as system of linear inequalities (linear program) with circuit node voltages as free variables. The LOP model parameters are obtained from device lookup tables (LUTs) from a single DC simulation. The linear program is solved to obtain valid voltage ranges of supply, input or biasing nodes. Practical examples show that this method provides fast analysis of device constraints with good accuracy over a wide range of CMOS technologies without numerous, time-consuming circuit simulations. Therefore it is well suited for analog design automation applications.
Date of Conference: 24-26 June 2010