By Topic

Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kuen-Jong Lee ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Jing-Jou Tang

In this paper we present two accurate and efficient modeling techniques for CMOS circuits to enhance the performance of test generation and fault simulation for bridging faults. The first one is a fault modeling technique for inter-gate bridging faults. The second one is an accurate threshold determination method. The accuracy of our model is achieved because all the following factors, including device parameters, voltage operation range of each logic value, resistance of ON-transistors, resistance of bridging faults, and test patterns are considered. The efficiency is achieved due to the simplicity of the solution methods that require no complex circuit level simulation. Experimental data show that SPICE like accuracy can be efficiently achieved

Published in:

Test Symposium, 1996., Proceedings of the Fifth Asian

Date of Conference:

20-22 Nov 1996