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Linearity improvement base on digital foreground calibration algorithm for a ultra high-speed analog-to-digital converter

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6 Author(s)
Ruitao Zhang ; National Laboratory of Analog IC's, Chongqing 400060, China) ; Jinshan Yu ; Zhengping Zhang ; Yonglu Wang
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In this paper, a digital calibration algorithm for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The spice simulation result shows the digital foreground calibration algorithm can efficiently improve the linearity of the ADC.

Published in:

2010 International Conference on Anti-Counterfeiting, Security and Identification

Date of Conference:

18-20 July 2010