Referenced Items are not available for this document.
This paper proposes a method of formal verification of self-testing (ST) property of combinational circuits using logic function manipulation. In this method we show that the problem of verification of ST property can be transformed to satisfiability problem of a decision function formed from characteristic functions of the circuit's output code words. Then the problem can be resolved using binary decision diagrams (BDD) efficiently. Experimental results show the effectiveness of the proposed method
Published in:
Test Symposium, 1996., Proceedings of the Fifth Asian
Date of Conference: 20-22 Nov 1996
- Page(s):
- 119 - 122
- Meeting Date :
- 20 Nov 1996-22 Nov 1996
- ISSN :
- 1085-7735
- Print ISBN:
- 0-8186-7478-4
- INSPEC Accession Number:
- 5565442
- Conference Location :
- Hsinchu
- Digital Object Identifier :
- 10.1109/ATS.1996.555147
- Product Type:
- Conference Publications
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