Cart (Loading....) | Create Account
Close category search window
 

Concurrent error detection and fault location in a fast ATM switch

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Yoon-Hwa Choi ; Dept. of Comput. Eng., Hongik Univ., Seoul, South Korea ; Pong-Gyou Lee

In this paper, we present a concurrent error detection and fault location technique for a fast ATM switch. The switch architecture has multiple data and control planes, each of which has an identical banyan topology. Cell headers are routed via the control planes to reserve their routing paths on the data planes. Multiplicity of data planes for enhancing performance is utilized to detect errors and locate faults during normal operation. An efficient algorithm is developed to locate faulty links or switching elements while normal switching operations are being performed. The identified faulty data planes can also be made usable for cell transmission

Published in:

Test Symposium, 1996., Proceedings of the Fifth Asian

Date of Conference:

20-22 Nov 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.