By Topic

Methodology for trench capacitor etch optimization using voltage contrast inspection and special processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Patterson, O.D. ; Semicond. R&D Center, IBM, Hopewell Junction, NY, USA ; Zhou, X.J. ; Takalkar, R.S. ; Hawkins, K.V.
more authors

Embedded DRAM will play a much larger part in IBM server microprocessors for new SOI technologies. Etch of a deep trench (DT) into the substrate, which is used to form the capacitor, is a complicated multi-step process. One of the key elements is etch of the buried oxide layer. Voltage contrast (VC) inspection is used to detect defective DTs and can differentiate between opens in the buried oxide and those in the oxide hard mask. So these defects have a VC signal, special processing is needed to seal off the SOI layer. The process of finding the right beam conditions to detect the opens in the buried oxide, which are very subtle, is described. Failure analysis of these defects is also presented.

Published in:

Advanced Semiconductor Manufacturing Conference (ASMC), 2010 IEEE/SEMI

Date of Conference:

11-13 July 2010