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Evaluating the system in early design steps is critical for an efficient design of Multi-Processor SoCs (MPSoC). When the number of processors grows, the simulation time tends to increase exponentially. Native co-simulation has been proposed to obtain performance estimations with sufficient accuracy while requiring short simulation times. In MPSoC architectures buses often become the most important bottleneck. In order to overcome this drawback, L2 caches are usually added to reduce the bus traffic. Thus, modeling the impact of second level caches is an essential issue to evaluate the overall performance system. However, to the best of our knowledge, no solutions for L2 cache modeling are supported in existing native co-simulation techniques. As this paper shows, the L1 cache models for native co-simulation in the literature only considers information about data and instruction locality, not complete, real memory addresses, while L2 caches require the complete physical addresses. Thus, an address translation is needed. In this paper an efficient technique to obtain the physical address, improving previous modeling solutions for L1 caches, is proposed. Furthermore, a high-level L2 cache model has been developed and integrated in a native co-simulation environment.