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This brief presents an innovative high-speed context-adaptive variable-length encoder. First, a direct forward algorithm rather than backward tracking is proposed to compute the coding parameters. The forward computation without data reordering can shorten the latency time and the processing cycle. Based on the algorithm, the real-time chip is designed with a parallel structure and pipelined control, which can encode one codeword per cycle. The maximum processing time for one block is the number of nonzero coefficients (NC)+4 cycles. The output bit rate can achieve 125 M/s when implemented with 0.18- μm CMOS technology. The chip occupies about 15 k gates, and the power dissipation is about 5.38 mW.