By Topic

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Kailash Chandrashekar ; Department of Electrical Engineering, Arizona State University, Tempe, AZ, USA ; Marco Corsi ; John Fattaruso ; Bertan Bakkaloglu

A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18-μm CMOS process and occupies a die area of 1.9 mm2.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:57 ,  Issue: 8 )