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The laser energy thresholds for SEU for SOI 1-Mbit SRAMs built in Sandia's 0.35-μm SOI technology were measured using carrier generation by two-photon absorption. The laser measurements were correlated to heavy-ion threshold LET measurements to determine an empirical relationship between laser energy threshold and heavy-ion threshold LET. This empirical relationship was used to estimate the threshold LETs for other circuits built in Sandia's 0.35-μm SOI technology and SRAMs built in IBM's 45 and 65-nm SOI technologies. For an ASIC built in Sandia's 0.35-μm SOI technology the estimated threshold from laser measurements was close to the measured heavy-ion threshold LET. However, for a dual-port SRAM also built in Sandia's 0.35-μm SOI technology and for the 45- and 65-nm IBM SOI SRAMs, the threshold LETs estimated from laser measurements did not correlate to the measured heavy-ion threshold LETs. For the IBM SRAMs, the likely cause of the discrepancy between the threshold LETs estimated from laser measurements and the threshold LETs measured by heavy-ion testing is due to the laser pulse simultaneously injecting charge into multiple transistors within a memory cell and/or in adjacent memory cells. This is due to the relatively large size of the laser spot size compared to the size of the SEU sensitive volume of the IBM SOI devices. The hardness assurance implications of these results are discussed.