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A 90 nm Bulk CMOS Radiation Hardened by Design Cache Memory

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4 Author(s)
Xiaoyin Yao ; Sch. of Electr., Comput. & Energy Eng., Arizona State Univ., Tempe, AZ, USA ; Clark, L.T. ; Patterson, D.W. ; Holbert, K.E.

A RHBD high performance cache fabricated on 90 nm bulk CMOS is presented. Test silicon cache data arrays can read and write at 1.02 GHz. Irradiation to 2 Mrad(Si) negligibly impacts standby current. The cache is write-through, and relies on error checking to allow cache invalidation when single event upsets or potential single event transients are detected. The write-through cache architectural state will then naturally be reloaded by the ensuing microprocessor operations. Single cycle invalidation is supported. Single event error ion beam test results are presented, as is a description of measured single event effects in array and peripheral circuits and their mitigation by the design.

Published in:

Nuclear Science, IEEE Transactions on  (Volume:57 ,  Issue: 4 )

Date of Publication:

Aug. 2010

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