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Scalable shared-memory multiprocessor architectures

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4 Author(s)
Thakkar, S. ; Sequent Comput. Syst., Beaverton, OR, USA ; Dubois, Michel ; Laundrie, A.T. ; Sohi, G.S.

Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop new parallel applications or to move existing applications from a uniprocessor to a parallel system. Two architectural variations of bus-based systems are described: multiple-bus and hierarchical architectures.<>

Published in:

Computer  (Volume:23 ,  Issue: 6 )