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A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization

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3 Author(s)
Tony Shuo-Chun Kao ; Edward S. Rogers, Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada ; Faisal A. Musa ; Anthony Chan Carusone

This paper presents an optical receiver with a monolithically integrated photodetector in 0.18-μm CMOS technology using a combination of spatially modulated light (SML) detection and an analog equalizer. A transimpedance amplifier employing negative Miller capacitance is introduced to increase its bandwidth without causing gain peaking. To provide sufficient reverse-bias voltage to the photodetector's p-n junction, the transimpedance amplifier is operated with a 3.3-V supply, while the rest of the circuit blocks is powered with a 1.8-V supply. The on-chip SML detector achieves a net responsivity of 0.052 A/W. Occupying a core area of 0.72 mm2, the fully integrated optical receiver achieves 4.25 and 5 Gbits/s with power consumption values of 144 and 183 mW, respectively.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:57 ,  Issue: 11 )