Referenced Items are not available for this document.
In this brief, we present an efficient design of a shared architecture to compute two 8-point Daubechies wavelet transforms. The architecture is based on a two-level folded mapping technique that is developed on the factorization and decomposition of transform matrices exploiting the symmetrical structure. The chip occupies a 2.08-mm2 silicon area, runs at 100 MHz, and consumes 4.51 mW of power in 0.18-m CMOS technology.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on
(Volume:57
,
Issue:
9
)
Date of Publication: Sept. 2010
- Page(s):
- 716 - 720
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 11523338
- Digital Object Identifier :
- 10.1109/TCSII.2010.2056111
- Product Type:
- Journals & Magazines
- Date of Publication :
- 16 August 2010
- Date of Current Version :
- 13 September 2010
- Issue Date :
- Sept. 2010
- Sponsored by :
- IEEE Circuits and Systems Society
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