Skip to Main Content
In charge-pump phase-locked loops (CP-PLLs), the reference signal samples the phase delay between reference and feedback signals. When a frequency divider is present in the loop, the spectrum folding of the voltage-controlled oscillator phase noise caused by the inherent subsampling operation adds a relevant contribution to the in-band output noise. This brief elaborates the discrete-time linear model of PLLs to take into account spectrum folding and provides a simple equation for the estimation of the output noise. The closed-form expressions are validated on the basis of behavioral simulations of a third-order CP-PLL.