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Compiler-directed cache management in multiprocessors

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2 Author(s)
Hoichi Cheong ; Illinois Univ., Urbana, IL, USA ; Veidenbaum, A.V.

The necessity of finding alternatives to hardware-based cache coherence strategies for large-scale multiprocessor systems is discussed. Three different software-based strategies sharing the same goals and general approach are presented. They consist of a simple invalidation approach, a fast selective invalidation scheme, and a version control scheme. The strategies are suitable for shared-memory multiprocessor systems with interconnection networks and a large number of processors. Results of trace driven simulations conducted on numerical benchmark routines to compare the performance of the three schemes are presented.<>

Published in:

Computer  (Volume:23 ,  Issue: 6 )