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Dual- k Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs

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3 Author(s)
Virani, H.G. ; Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India ; Adari, R.B.R. ; Kottantharayil, A.

A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO2, Al2O3, and HfO2 gate dielectrics. The structure is optimized for the on-state current without degrading the off-state current or the subthreshold slope.

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Electron Devices, IEEE Transactions on  (Volume:57 ,  Issue: 10 )