By Topic

Enhanced performance of vertical double gate MOSFET (VDGM) with oblique rotating implantation (ORI) method

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Saad, I. ; Sch. of Eng. & IT, Univ. Malaysia Sabah, Kota Kinabalu, Malaysia ; Riyadi, Munawar A. ; Zul Atfyi, F.M.N. ; Hamid, A.M.A.
more authors

An enhanced performance of vertical double gate MOSFET (VDGM) structure was revealed by adopting the oblique rotating ion implantation (ORI) method. The device structure was simulated based on TCAD tools and verified by good matching data with the published experimental results. With ORI method a symmetrical self-aligned source/drain regions over the silicon pillar and sharp vertical channel profile was observed. With Lg = 50nm, the VT is 0.96V in double gate and increased to 1.2V in single gate structure. The sub threshold swing, S = 81.9 mV/dec and S = 87.7 mV/dec were obtained for double and single gate devices respectively. Similarly, large IDsat = 370μA/μm was observed for double gate compared to single gate device. By scaling the Lg into 50nm, the VT remains almost the same when the Lg is larger than 80nm. However, it decreases rapidly when scaled down to 50nm. The leakage current increases rapidly when the Lg is scaled down to 100nm and beyond. However, the ratio of ION - IOFF is seen to be increases even with shorter Lg. These results indicates that ORI method is essential for overcoming various SCE as scaling the channel length down to nanometer regime.

Published in:

Semiconductor Electronics (ICSE), 2010 IEEE International Conference on

Date of Conference:

28-30 June 2010