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Access scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and its optimization

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7 Author(s)
Yiran Chen ; Seagate Technology, 1280 Disc Dr., MN, 55379, USA ; Xiaobin Wang ; Wenzhong Zhu ; Hai Li
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In this work, we study the access (read and write) scheme of the newly proposed Multi-Level Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) from both the circuit design and architectural perspectives. Based on the physical principles of the resistance state transition of MLC STT-RAM, we proposed a read circuitry based on Dichotomic search algorithm and three write schemes with various design complexities - simple, complex, and hybrid schemes. The circuit and architectural level evaluations were conducted to analyze the power and performance tradeoffs in each proposed write mechanisms of MLC STT-RAM.

Published in:

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

Date of Conference:

1-4 Aug. 2010