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An ultra-low power 200 MHz-1 GHz programmable frequency divider with novel clear/preset d-latch

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2 Author(s)
Khan, T. ; Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada ; Raahemifar, K.

This paper presents a low power programmable frequency divider for use in implantable electronics operating in the 402 MHz to 405 MHz Medical Implant Communication Service (MICS) frequency band. The programmable divider was designed in IBM CMRF8SF 130 nm CMOS technology and simulated using Cadence Spectre circuit simulator. Subthreshold-source coupled logic has been used in this circuit for the first time to allow for gates to operate with very low current consumption and maintain a useful output signal swing, and exhibits performance comparable to or exceeding that of previously published designs. Simulation results show that the total power consumption of the divider is 210 μW from a 0.7 V supply, and operates up to 1 GHz. The programmable divider utilizes a novel d-latch with clear/preset functionality. The functionality is demonstrated by designing the divider for use in a MICS frequency synthesizer to select from one of the 10 300 kHz channels in the spectrum.

Published in:

Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Date of Conference:

1-4 Aug. 2010

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