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With modern CMOS technology already close to approaching the limits of lithography, serious doubts exist over the ability of the standard CMOS ASIC design approach to deliver the required complexity, integration density and computational capability. This has prompted increasing research in novel non-CMOS devices to address the issues of modern day computing. This paper presents an investigation into the feasibility of recently proposed Ballistic Deflection Transistors (BDT) for future generation Terahertz computing. By means of Monte Carlo modeling we show that the device is capable of entering into the THz range at room temperature. We propose an analytical expression which can be used to describe an accurate behavioral model of BDT in Verilog-A, to serve as the first generation Predictive Technology Model for the Ballistic Deflection Transistor. We conclude presenting structures for various logic gates developed using the BDT.