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This paper analyses the use of folded cascode Low Noise Amplifiers (LNAs) for the implementation of multistandard wireless transceivers. The proposed LNA consists of a two-stage topology made up of a folded cascode and simple-stage amplifiers that use NMOS-varactor based tuning networks to make the operating frequency continuously programmable. The circuit has been designed and implemented in a 90-nm CMOS technology in order to cope with the requirements of GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b/g) standards. Practical design issues are analysed, considering the effect of circuit parasitics associated to both the chip package and integrated inductors, capacitors and varactors; as well as technology parameter deviations. The circuit design is optimized using genetic algorithms to achieve the required specifications with adaptive power consumption. Layout-extracted simulation results demonstrate a correct operation of the proposed circuit, showing a continuous tuning of Noise Figure (NF) and S-parameters within the 1.85-2.48GHz band, featuring NF<;3.8dB, S21 >12dB and IIP3> -12dBm, with an adaptive power dissipation between 13.3mW and 23.1mW from a 1-V supply voltage.
Date of Conference: 1-4 Aug. 2010