By Topic

Bit-Wise MTNCL: An ultra-low power bit-wise pipelined asynchronous circuit design methodology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Liang Zhou ; Dept. of Electr. Eng., Univ. of Arkansas, Fayetteville, AR, USA ; Smith, S.C. ; Jia Di

This paper develops an ultra-low power design methodology for bit-wise pipelined asynchronous circuits, called bit-wise MTNCL, which combines multi-threshold CMOS (MTCMOS) with bit-wise pipelined NULL Convention Logic (NCL) systems. Compared to original NCL circuits implemented with all low-Vt and high-Vt transistors, respectively, it provides the leakage power advantages of the all high-Vt NCL implementation with a reasonable speed penalty compared to the all low-Vt design, requires less energy/operation, and has no area overhead.

Published in:

Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Date of Conference:

1-4 Aug. 2010