By Topic

Systolic-array architecture for 2D IIR Wideband dual-beam space-time plane-wave filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wijenayake, C. ; Electr. & Comput. Eng., Univ. of Akron, Akron, OH, USA ; Madanayake, A. ; Bruton, L.T.

A spatio-temporal 2D IIR broadband plane-wave filter having 2 user-selectable passbands is proposed using the concept of 2D network resonance. The plane-wave filter is capable of the highly-selective directional enhancement of 2 far-field plane-waves in the presence of undesired waves at different directions of arrival. A massively-parallel systolic-array processor architecture is proposed for the real-time VLSI implementation of the filter. The architecture is designed, simulated, and implemented as a prototype clocked at 50 MHz, using a Xilinx Virtex-4 Sx35-10ff668 FPGA device. The proposed systolic-array delivers a real-time throughput of one-frame-per-clock-cycle (OPFCC) which implies 50 million linear frames per second. The design is simulated (for a 32 element array) and tested on-chip (for an 18-element array) using 2D impulse- and frequency-responses, and using multi-directional broadband plane-wave test sequences.

Published in:

Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Date of Conference:

1-4 Aug. 2010