By Topic

4.2K CMOS circuit design for digital readout of Single Electron Transistor electrometry

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Das, Kushal ; Centre for Quantum Comput. Technol., Univ. of New South Wales, Sydney, NSW, Australia ; Lehmann, T. ; Rahman, M.T.

We present the perspective of CMOS electronics as a candidate for the readout purposes of sensing devices such as the Single Electron Transistor (SET) at very low temperature. Fully Depleted Silicon on Insulator (FD-SOI) CMOS devices are less susceptible to low temperature anomalies compared to bulk devices. The electrical characteristics of a typical SET are too small in comparison to usual current/voltage levels for MOS circuits and thus imposes new complications in circuit design. We present a digital readout scheme of the SET best suited for scalable design. The circuit is implemented with commercial 0.5μm SOI CMOS process operating at 4.2K. The simulation results show successful detection of 200pA drain current of an SET biased at 10μV with 15μs detection speed and static power dissipation less than 45μW.

Published in:

Circuits and Systems (MWSCAS), 2010 53rd IEEE International Midwest Symposium on

Date of Conference:

1-4 Aug. 2010