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A systems approach to verification using hardware acceleration

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4 Author(s)
Kumar, S. ; Freescale Semicond. Pvt. Ltd., Noida, India ; Shanbhag, S. ; Mongia, M. ; Verma, G.

The increasing complexity of system-on-chip devices has made verification of these devices an extremely difficult task. Additionally, there is the pressure of time-to-market that is faced by all semiconductor companies. Some of the functional complexity of such devices has made it necessary to run system level sequences that were typically run only in post-silicon phase in the pre-silicon stages. However, the effective speeds of simulators used during functional verification do not lend well to running system level tests. In this paper we will describe how a hardware accelerator was used to execute system level tests. We will share some of the results seen and some of the design issues that were detected using such an approach. We have illustrated this approach choosing three distinct areas of (i) secure boot, (ii) built-in-self-test sequences, and (iii) scan testing. We also believe that going to a system level approach using hardware acceleration helps to find several difficult corner case issues that remain undetected using other verification approaches.

Published in:

Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on

Date of Conference:

3-4 Aug. 2010