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Along with decrement in size of nanoelectronic devices, they are more prone to the effects of transient faults. Therefore, investigating the effects of such faults is of great importance. Due to high count of transistors in nanoelectronic devices, performing simulation by HSPICE is a time consuming process. Hence, several mathematical models have been proposed. However, our proposed model is simple while being more precise considering factors such as glitch amplitude and rise-fall time mismatch. The predictions of our model are 98% close to those of HSPICE simulation ones in average.
Date of Conference: 3-4 Aug. 2010