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FPGA implementation of compressive sampling for sensor network applications

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3 Author(s)
Yan Wang ; ECE Dept., Hong Kong Univ. of Sci. & Technol., Hong Kong, China ; Bermak, A. ; Boussaid, F.

This paper examines the implementation considerations of Compressive Sampling (CS) in Field Programmable Gate Array (FPGA) and proposes computation-free linear projection implementation for CS encoding in imaging applications. A simplified sensing matrix is implemented to eliminate the multiplication and summation processes in the sensing stage. This sensing paradigm does not require all pixels in an image to be fully captured before being projected into measurements. This is in contrast with the case when Gaussian or Noiselet sensing matrix is applied. Though the recovered image obtained by this work is 2.64dB lower in PSNR than that of the optimal Gaussian matrix, the problem of Saturation noise caused by significantly increased dynamic range of the measurements compared with the original pixel value could be avoided in the practical applications. This compressive sampling scheme is implemented in FPGA and is interfaced with a CMOS imager for experimental validation.

Published in:

Quality Electronic Design (ASQED), 2010 2nd Asia Symposium on

Date of Conference:

3-4 Aug. 2010