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Embedded multi-core architectures will require a higher bandwidth and scalable Networks on Chip (NoC) to sustain an increasingly demanding communication load in both image and signal processing areas. Corner turns (or matrix transpose) are frequently used in such applications and require special attention due to their all-to-all communications patterns. To address such issues, we propose a variation of a hypercube NoC topology and evaluate it using a circuit switching based routing algorithm. We also propose a new exhaustive partially profitable backtracking algorithm, and we show that it outperforms existing protocols by 40% and by 15% on average for image and signal processing applications on the same topology.