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Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage

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4 Author(s)
Behzad Ebrahimi ; Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran ; Masoud Rostami ; Ali Afzali-Kusha ; Massoud Pedram

In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:19 ,  Issue: 10 )