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A Silicon Interposer With an Integrated {\rm SrTiO}_{3} Thin Film Decoupling Capacitor and Through-Silicon Vias

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3 Author(s)
Shibuya, A. ; Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan ; Ouchi, A. ; Takemura, Koichi

A silicon interposer with an integrated with SrTiO3 (STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm2 was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm2 area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.

Published in:

Components and Packaging Technologies, IEEE Transactions on  (Volume:33 ,  Issue: 3 )