By Topic

Design and implementation of a radiation tolerant on-board computer for science technology satellite-3

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Dong-Soo Kang ; Dept. of Comput. Eng., ChungNam Nat. Univ., Daejeon, South Korea ; Kyoung-Son Jhang ; Dae-Soo Oh

This paper describes the design and implementation of a radiation tolerant on-board computer (OBC) for the science and technology satellite-3 (STSAT-3). SRAM-based FPGAs are replacing traditional integrated circuits for space applications. However, it is difficult to employ the approach in space applications without radiation tolerant schemes to deal with the radiation effects such as single event upset (SEU). To mitigate the SEU effect, we apply a triple modular redundancy (TMR) scheme to the STSAT-3 OBC based on FPGA. Although there is an overhead in area, power and minimum clock period, we notice through a radiation test in an irradiation facility that our TMR based OBC is immune to the radiation environments up to a proton energy of 20.3MeV. The radiation environment of the test is expected to be more severe than the environment in which STSAT-3 is to be located.

Published in:

Adaptive Hardware and Systems (AHS), 2010 NASA/ESA Conference on

Date of Conference:

15-18 June 2010