By Topic

High Resolution Application Specific Fault Diagnosis of FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Tahoori, M.B. ; Dept. of Comput. Sci., Inst. of Comput. Sci. & Eng. (ITEC), Karlsruhe, Germany

High resolution diagnosis plays a critical role in silicon debug and yield improvement. Application-dependent diagnosis is also a key component in online testing and adaptive computing. In this paper, a new technique for high resolution localization of faults in the interconnects and logic blocks of an arbitrary design implemented on a field-programmable gate array (FPGA) is presented. This work is complementary to application-independent detection methods for FPGAs. This technique can uniquely identify any single bridging, open, or stuck-at fault in the interconnect as well as any single functional fault, a fault resulting a change in the truth table of a function, in the logic blocks. The number of test configurations for interconnect diagnosis is logarithmic to the size of the mapped design, whereas logic diagnosis is performed in only one test configuration with less than 5% overhead of built-in self diagnosis. These techniques have been further extended for multiple fault diagnosis.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 10 )