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Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits

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2 Author(s)
Irith Pomeranz ; School of Electrical and Computer Engineering, Purdue University, W. Lafayette ; Sudhakar M. Reddy

We define the strength of a test for transition faults based on the number of fault effects that can disappear without causing the test to lose the detection of target faults. The removal of fault effects represents the uncertainty created by pattern-dependent effects that can slow-down or speed-up signal-transitions, thus causing fault effects predicted by logic-level simulation to disappear. A test set that consists of higher-strength tests is less susceptible to these effects. We demonstrate that a transition fault test set with higher-strength tests also detects more path delay faults, which represent delay defects that were not targeted during test generation.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:19 ,  Issue: 10 )