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Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs

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2 Author(s)
Nain, R.K. ; Electr. & Comput. Eng. Dept., Portland State Univ., Portland, OR, USA ; Chrzanowska-Jeske, M.

We present a placement-aware 3-D floorplanning algorithm that considers 3-D-placement of logic gates inside modules for wirelength minimization. It allows designers to introduce and evaluate an assignment of vertically-aligned parts of the same module to different device layers. A set of vertical constraints is derived on sequence pairs of different device layers that reduces the solution space, and a fast packing algorithm with vertical constraints enables quick floorplan evaluation. Experimental results on MCNC and GSRC benchmarks show that our algorithm can generate a good floorplanning solution with reduced wirelength inside modules and optimized footprint area while controlling the number of vias. Compared to the existing state-of-the-art 3-D floorplanning algorithms, our tool reduces the system level total wirelength by 9.8%.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 9 )

Date of Publication:

Sept. 2011

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