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A High Gain, High Power K-Band Frequency Doubler in 0.18 \mu{\rm m} CMOS Process

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2 Author(s)
Jung-Hau Chen ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Huei Wang

A K-band frequency doubler with a current-reuse technique implemented using 0.18 μm CMOS process is presented in this letter. This frequency doubler exhibits a high conversion gain of -0.5 ~ -4.5 dB from 18 to 26 GHz with 0 dBm input drive power, and good fundamental rejection of 30 to 50 dB. The dc power consumption is 18.2 to 20.8 mW, and the chip size is 0.54 × 0.53 mm2. To the author's knowledge, this frequency doubler achieves the highest conversion gain and output power among all K-band CMOS frequency doublers to date.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:20 ,  Issue: 9 )