Referenced Items are not available for this document.
The RF performance of vertical nanowire metal-oxide-semiconductor field-effect transistors in realistic layouts has been calculated. The parasitic capacitances have been evaluated using full 3-D finite-element method calculations, combined with self-consistent Schrödinger-Poisson calculations for the intrinsic gate capacitances. It is shown that a performance comparable to planar FETs can be achieved in the vertical geometry by scaling the nanowire diameter and the wire-to-wire separation.
Published in:
Nanotechnology, IEEE Transactions on
(Volume:10
,
Issue:
4
)
Date of Publication: July 2011
- Page(s):
- 668 - 673
- ISSN :
- 1536-125X
- INSPEC Accession Number:
- 12141671
- Digital Object Identifier :
- 10.1109/TNANO.2010.2064783
- Product Type:
- Journals & Magazines
- Date of Publication :
- 09 August 2010
- Date of Current Version :
- 07 July 2011
- Issue Date :
- July 2011
- Sponsored by :
- IEEE Nanotechnology Council
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