By Topic

Package clock distribution design optimization for high-speed and low-power VLSIs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Qing Zhu ; Intel Corp., Santa Clara, CA, USA ; Simon Tam

With continually increased difficulties of the clock distribution in high speed microprocessors and application-specific integrated circuits (ASICs), the package clock distribution shows very promising advantages. The concurrent design of chip and package will provide the optimal design of a clock network by taking the advantages of package layers. The package layers provide 1000 times less wire resistance and 10 times less wire capacitance than those of interconnects on chip. Therefore, it is more beneficial to route the global clock network on package. The implementation issues of the package clock distribution are described in this paper, including the electrostatic discharge (ESD) circuit design for local clock buffers and transmission line noise suppression for package clock trees

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:20 ,  Issue: 1 )