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Trench gate integration into planar technology for reduced on-resistance in LDMOS devices

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4 Author(s)
Erlbacher, T. ; Fraunhofer Inst. for Integrated Syst. & Device Technol., Erlangen, Germany ; Rattmann, G. ; Bauer, Anton J. ; Frey, L.

In this paper, we report on the reduction of device resistance by up to 49% in junction isolated lateral double diffused metal-oxide-semiconductor (LDMOS) field effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on different state-of-the-art LDMOS field effect transistor concepts with and without a reduced surface field extension (buried p-well) for high voltage applications used for standard IC and ASIC manufacturing processes in commercially available foundry processes. A limited number of additional process steps are required for manufacturing such a device, and the well implants can remain unchanged. By a straight-forward combination of trench gate with planar gate topology the device resistance can be reduced from 217mΩ·mm2 down to 110mΩ·mm2 for an underlying 50V LDMOS device with a 3.3V gate oxide. The robustness of trench gate integration into existing planar gate technology is demonstrated by fully maintaining the specified blocking properties.

Published in:

Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on

Date of Conference:

6-10 June 2010

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