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EMI effects and timing design for increased reliability in digital systems

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2 Author(s)
Chappel, J.F. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; Zaky, S.G.

The failure modes of digital circuits subjected to low levels of electromagnetic interference (EMI) are examined. While low-level EMI will not cause static failures (false switching), it may cause dynamic failures by changing the propagation delays of critical signals. A parameter called delay margin is introduced to define the maximum allowable changes in propagation delay under which the circuit will continue to operate reliably. Experimental results are reported in which circuit immunity to EMI is shown to increase significantly when the delay margin is maximized. It is also shown that delay-insensitive circuits have infinite delay margins and are therefore immune to low-level EMI. It was observed experimentally that an oscillating loop subjected to EMI can become phase locked to the frequency of the interference. The second part of the paper describes a synchronization scheme that takes advantage of this phenomenon. The proposed scheme can be used to reduce errors due to synchronizer metastability on communication links between synchronous and asynchronous systems. A reference signal derived from the clock of the synchronous system is injected into a handshake loop, causing the data transfer rate to be locked to a subharmonic of the clock frequency. Both simulation and experimental results are given, showing that stable operation can be achieved over a wide range of parameters

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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:44 ,  Issue: 2 )