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An implementation of energy efficient multi-performance processor for real-time applications

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2 Author(s)
Chengjie Zang ; Syst. LSI Res. Center, Kyushu Univ., Fukuoka, Japan ; Ishihara, T.

Multi-performance processor reduces the energy consumption by using lower supply voltage in CPU core and reducing the number of cache ways activated when applications do not need the peak performance of the processor. In this paper, the design results of a multi-performance processor is presented, which has two processing elements, PE-H and PE-M. The design flow of finding minimum VDD for PE-M is shown. The processor is implemented by commercially available 0.18 μm process technology. PE-H and PE-M are synthesized using cell libraries characterized with 1.8V and 1.0V, respectively. Post-layout simulation is performed to evaluate energy consumption and performance of the processor. The experimental results show that a PE with 1.0V supply voltage takes more than 50% smaller energy consumption and longer execution time compared with those of a PE with 1.8V supply voltage. The experiments also demonstrate that the selective-way instruction cache contributes for saving the energy consumption. The results show that lower associative cache consumes lower energy while takes larger execution time. The energy efficiency of the selective-way cache technology depends on the type of benchmark program. At last, the paper shows the specifications of the processor. The processor with two PEs can save the energy consumption without losing peak performance of the processor. The area overhead for having two PE cores is only 6.88% of the total chip area.

Published in:

Green Circuits and Systems (ICGCS), 2010 International Conference on

Date of Conference:

21-23 June 2010