Close category search window
 

Low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Wang, T. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA ; Temes, G.C.

A low-power parasitic-insensitive switched-capacitor (SC) integrator is proposed for ΔΣ ADCs. Compared to the conventional SC integrator, the new one achieves much lower power dissipation for the same sampling noise specification. A cancellation technique is used to reduce the nonlinearity of the integrator. An effective ΔΣ ADC topology is described which can incorporate the new integrator. Simulation shows that high linearity can be achieved by the new integrator, while consuming very low power.

Published in:
Electronics Letters  (Volume:46 ,  Issue: 16 )

Date of Publication: August 5 2010

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.