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A low-power parasitic-insensitive switched-capacitor (SC) integrator is proposed for ΔΣ ADCs. Compared to the conventional SC integrator, the new one achieves much lower power dissipation for the same sampling noise specification. A cancellation technique is used to reduce the nonlinearity of the integrator. An effective ΔΣ ADC topology is described which can incorporate the new integrator. Simulation shows that high linearity can be achieved by the new integrator, while consuming very low power.
Date of Publication: August 5 2010