By Topic

The light at the end of the CMOS tunnel

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
1 Author(s)
Nassif, S.R. ; IBM Res., Austin, TX, USA

In spite of numerous predictions to the contrary, Silicon technology is marching along past the 22nm node and on to ever finer dimensions. Innovations at the technology device, circuit and system levels continue to enable us to scale in spite of what sometime appear to be insurmountable problems in power, lack of performance, manufacturability and so on. To a large degree, these innovations are necessary because no substitute technology has been found as yet and, in fact, it does not appear likely that any such technology will become practical this decade. This leaves us with the need to anticipate and predict the near and medium term futures of CMOS for the next handful of technology nodes. This talk will focus on doing just that, and will show how an important new constraint on future system scaling is circuit resilience. Resilience is the ability of circuits to operate in spite of challenges like noise, difficult environmental conditions, ageing and manufacturing imperfections. These factors conspire to cause transient or permanent errors that are indistinguishable from traditional "hard" faults typically caused by defects during fabrication. Without significant innovation at the circuit and system levels, the probability of these events can rise quite dramatically. In the area of SRAM, such phenomena have existed for the last three or four technology nodes, but significant investments in this area have indeed allowed continued system level scaling with ever larger on-chip memories. As these same phenomena start attacking integrated circuits more pervasively, there is an urgent need for research and development in this area to avert the problems certain to arise with increased defect rates. This keynote paper explores the link between the old subject of manufacturing variability and its well-known impact on circuit performance, and the new subject of the way that same variability -in the extreme- can cause complete circuit failure. With care, we will find that t- e light at the end of the CMOS tunnel is the opening of new opportunities to enrich CMOS with new technologies like MEMS, optics, sensors and even biological devices. Otherwise, that light is likely to be another train...

Published in:

Application-specific Systems Architectures and Processors (ASAP), 2010 21st IEEE International Conference on

Date of Conference:

7-9 July 2010