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A low-power VLSI implementation for variable block size motion estimation in H.264/AVC

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2 Author(s)
Peng Li ; Department of Electrical and Computer Engineering, University of Minnesota Duluth, Duluth MN, 55812, USA ; Hua Tang

Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for full-search VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput. The proposed architecture has been implemented and tested in Xilinx XtremeDSP Video Starter Kit Spartan-3ADSP 3400A Edition, and also verified using standard cell approach in UMC 0.18μm CMOS technology. Compared to other VBSME designs that give optimal solutions of Motion Vectors (MV), the proposed design can save power consumption by more than 56%.

Published in:

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

Date of Conference:

May 30 2010-June 2 2010