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Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees

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2 Author(s)
Blad, A. ; Electron. Syst., Linkoping Univ., Linköping, Sweden ; Gustafsson, O.

In this work we consider high-speed FIR filter architectures implemented using, possibly pipelined, carry-save adder trees for accumulating the partial products. In particular we focus on the mapping between partial products and full adders and propose a technique to reduce the number of carry-save adders based on the inherent redundancy of the partial products. The redundancy reduction is performed on the bit-level to also work for short wordlength data such as those obtained from sigma-delta modulators.

Published in:

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Date of Conference:

May 30 2010-June 2 2010