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17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection

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7 Author(s)
Ohhata, K. ; Dept. of Electr. & Electron. Eng., Kagoshima Univ., Kagoshima, Japan ; Imamura, H. ; Ohno, T. ; Taniguchi, T.
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This paper describes the design and experimental results of a 17 Gb/s vertical-cavity surface-emitting laser (VCSEL) driver using a double-pulse asymmetric emphasis technique. In this technique, the first pulse compensates for the parasitic capacitances and the second pulse compensates for the ringing, which enables a good eye opening even when the data rate increases. A test chip fabricated using a 90-nm CMOS technology generates a clearly open optical eye at a data rate of 17 Gb/s, which is approximately twice the VCSEL bandwidth.

Published in:

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Date of Conference:

May 30 2010-June 2 2010